AMD Carrizo Technical Slides - New GPU, Highly Power Efficient Architecture and HDL

AMD recently unveiled the official technical slides (via SemiAccurate) on Carrizo APU (something that was leaked a few days back already) and I thought it would be a good idea to go over some of the last details subconscious in the technical showcase. Important pattern features such as the new High Density Library blueprint were showcased - something found ordinarily in GPU architecture. The integrated-GPU is newer than the one featured on "Kaveri." Information technology features 8 compute units (512 stream processors) based on Graphics CoreNext 1.3 architecture, with Drape and DirectX 12 API support, and H.265 hardware-acceleration.

AMD Carrizo APU A stock photo of the Carrizo die. @AMD Public Domain

Loftier Density Libraries, AVFS, More efficient GPU and More than in Carrizo

AMD's compages is very modular in nature. To quote themselves, information technology's built like lego. They tin can combine different cores to create different products nearly seamlessly and easily. Everything is built from the scratch up to have multiple configurations and mixing. This allows them to have a very dynamic roadmap - and also highly susceptible to change - giving them the freedom of being able to react to Industry as well. Keeping that in mind the new HDL (High Density Library ) characteristic of Carrizo is something that should take micro-architecture enthusiasts pretty excited well-nigh. Carrizo integrates the Southbridge on the SoC favoring single chip design to an MCM. Not to mention that the slides also testify the Soi3 state indicating that the processor will be capable of avant-garde power saving functions. Information technology goes without saying that Intel's implementation is superior just the Soi3 state allows AMD to approach the same level.

An interesting query now arises. The current design really makes the CPU a scrap more than GPU like than tradition. Obviously, the inverse could hold true for the GPU as well. The transistor choice states the same thing. I have a feeling we are looking at an architecture that was designed for the ground upwardly to support HSA. HSA is most a unified chip working exploiting parallel loads and this sounds like the perfect mixup to do just that. AMD has also employed something chosen Voltage Adaptive Operation or AVFS which tin allegedly reduce power consumption by effectually xix% for the CPU and x% for the GPU. Interestingly the concept of vdroop is relevant here. For those who donot know, vdroop is the calibrated feature of a die to reduce voltage supplied at a frequency jump to avoid over powering the cadre and accidentally supplying more electric current. Overclockers counter the feature by using something called Load Line Scale and this new feature appears to exist an advanced implementation of the same.

Lets talk HDL now, simply put, HDL is packing more metal layers in the same dice area. Something that is not only extensively used in GPU production but pretty common in the top silicon players. AMD'due south Carrizo APU uses eight layers. The downside of compressing layers is that the upper limit (or OC headroom) at higher clocks will be limited due to the confined infinite while offer more than power efficiency at lower clocks - and considering Carrizo targets the mobile segment, that is perfectly fine. It likewise means that Excavator is significantly more ability efficient while packing a smaller human foot print at the same fourth dimension - at present that's good architectural improvement.